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Specify, Check, Test, and Run for Safe and Efficient Parallelism

This project aims to ensure safe and efficient parallel computing by utilizing explicit annotations for disciplined shared memory: the programmer specifies the annotations that the software testing techniques and hardware design can exploit. These annotations are used by SafeSpeed components at all levels, from specification to run-time. DPJ, DPJizer, Accord, and AMP focus on the specification and checking, Penelope is used for testing, and DeNovo supports parallelization at run-time.

DPJ and DPJizer

Deterministic Parallel Java (DPJ) is based on the belief that all code should be deterministic (a fixed input always produces a fixed output) unless the programmer explicitly requests non-determinism. DPJ is a fully Java-compatible extension of sequential Java that is expressive enough for irregular, dynamic parallelism. The speedups it provides are close to hand-written Java programs. Semi-automatic porting of Java programs to DPJ can be done with DPJizer, an interactive Eclipse plug-in. DPJizer can often out-perform a human programmer.


The objective here is to create an annotation language, Accord, that allows the programmer to express a sharing strategy, verify that the annotation strategy is race condition-free, and test that a program respects that strategy. Accord will work with code in existing programming languages, express complete array regions, handle locks, and provide checks using both logical constraint solvers and run-time testing.


Annotations for Modular Parallelism (AMP) is based on DPJ and Accord. It assumes three things: the code will be written with C/C++ as a base sequential language, no memory violations are present, and no illegal type conversions will be specified. AMP requires that effects summaries are specified in terms of memory “regions” and have predicated effects that will allow conditional effects. In turn, it supports the expression of side effects on methods or tasks and checks for correct lock use by providing lock/data association.


Because concurrent programs are highly-complex and interleaved, testing even a single input for functional correctness is difficult, and nearly impossible to explore all possible executions. Penelope seeks to predict and select testing schedules (non-atomic runs are good candidates) that expose concurrency bugs. Current results are promising: no false positives were reported using Penelope and full reproductions (of modulo OS events, etc.) were possible.


DeNovo aims to create hardware that is scalable in power, complexity, and performance through disciplined, shared memory. Software under DeNovo features DPJ that focuses on deterministic codes. The end goal is a language-oblivious interface that will extend to non-deterministic legacy code. Hardware under DeNovo will feature cache coherence and consistency, a communication architecture, data-based layout, and off-chip memory. DeNovo’s current results indicate that it improves simplicity, extensibility, storage overhead, and performance.

For More Information

Contacts: Sarita Adve (, Vikram Adve (, and P. Madhusudan (

I2PC IL LogoI2PC Illinois is a joint research effort of the Illinois Department of Computer Science, Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory, with funding from corporate partner Intel. Its work is conducted by faculty members and graduate students from the computer science and electrical and computer engineering departments at the University of Illinois.