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I2PC Pathway to Easy Performance

Acrobatics aims to develop basic technologies in programming, translation, architecture, and tools to enable the development and execution of high-performance, power-efficient parallel code. It relies on high-level abstractions for parallel programming, together with compiler optimization and program synthesis techniques to generate code for architectures designed for programmability. The system is supported by a set of parallel programming tools for debugging, testing, refactoring, and performance/power monitoring.

Parallel Programming With HTAs

The focus of this research is designing data parallel operators to improve programmability and achieve high performance. Programs are seen as a sequence of data parallel operators. They resemble conventional serial programs, but with parallelism and locality encapsulated by the operators. The end results are programs that are better structured and are easier to port than programs in other notations. Moreover, determinacy (a given input produces a given output) is controlled. Data parallel operators written as pure functions result in deterministic programs. When non-determinacy is desired, it can be encapsulated inside the parallel operators while still protecting interactions with the global space.

Optimizations For Power

The objective is to minimize the energy consumption of a heterogeneous system under real-time constraints. The project focuses on a video post-processing application consisting of a pipeline of video processing filters. Reducing energy consumption in this pipeline involves two steps. The first is scheduling the different tasks on the correct processing units and at the appropriate voltage/frequency. Doing this allows us to take advantage of the heterogeneity of the system and reduce the cost of communication and the bandwidth requirements. The second step is developing program transformations that reduce communication and improve performance.

Bulk Multi-Core Architecture And Compilation System

The goal is to design a scalable multi-core architecture substrate that provides a highly programmable environment for the software layers in I2PC projects, while delivering high performance. It introduces a novel execution model based on the processors continuously executing Chunks of instructions. The Bulk Multi-core provides a novel scalable cache coherence support, thereby reducing the programmer’s burden of managing data sharing. This support is based on Chunks and Signatures. Chunks are sets of dynamically-contiguous instructions executed by the processor in an atomic manner. Signatures are hardware Bloom filters that summarize the footprint of addresses that a processor accesses. In addition to designing the architecture, this project aims to create a novel compiler for this machine. The compiler partitions the code into chunks and then performs aggressive transformations inside each chunk. This results in a higher performance than current compilers provide.

Parallel Programming Tools

The objective is to develop a comprehensive framework of hardware hooks and novel software algorithms to help develop and debug multithreaded codes. The tools are based on novel approaches and techniques to address difficult concurrency bugs. Data races, deterministic program replay, code section atomicity, and software-visible signatures are all areas of focus. We seek solutions that combine simple, versatile hardware primitives and the software that uses them. While some work relates to a processor that executes chunks like the Bulk Multi-Core, a major part of this effort applies to any shared-memory multi-core.

For More Information

I2PC IL LogoI2PC Illinois is a joint research effort of the Illinois Department of Computer Science, Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory, with funding from corporate partner Intel. Its work is conducted by faculty members and graduate students from the computer science and electrical and computer engineering departments at the University of Illinois.